The present invention relates to the recording and reproduction of binary data in disk storage systems for digital computers, particularly to a sampled amplitude read channel employing a post processor for generating error event error metrics for use in detecting and correcting errors made by a trellis sequence detector.
In disk drive storage devices for digital computers, such as magnetic and optical disk drives, sampled amplitude read channels employing partial response (PR) signaling with maximum likelihood (ML) sequence detection have provided a substantial increase in storage capacity by enabling significantly higher linear bit densities. Partial response signaling refers to a particular method for transmitting symbols represented as analog pulses through a communication medium. The benefit is that at the signaling instances (baud rate) there is no intersymbol interference (ISI) from other pulses except for a controlled amount from immediately adjacent, overlapping pulses. Allowing the pulses to overlap in a controlled manner leads to an increase in the symbol rate (linear recording density) without sacrificing performance in terms of signal-to-noise ratio (SNR).
Partial response channels are characterized by the polynomials
(1xe2x88x92D)(1+D)n
where D represents a delay of one symbol period and n is an integer. For n=1,2,3, the partial response channels are referred to as PR4, EPR4 and EEPR4, with their respective frequency responses shown in FIG. 1A. The channel""s dipulse response, the response to an isolated symbol, characterizes the transfer function of the system (the output for a given input). With a binary xe2x80x9c1xe2x80x9d bit modulating a positive dipulse response and a binary xe2x80x9c0xe2x80x9d bit modulating a negative dipulse response, the output of the channel is a linear combination of time shifted dipulse responses. The dipulse response for a PR4 channel (1xe2x88x92D2) is shown as a solid line in FIG. 1B. Notice that at the symbol instances (baud rate), the dipulse response is zero except at times t=0 and t=2. Thus, the linear combination of time shifted PR4 dipulse responses will result in zero ISI at the symbol instances except where immediately adjacent pulses overlap.
It should be apparent that the linear combination of time shifted PR4 dipulse responses will result in a channel output of +2, 0, or xe2x88x922 at the symbol instances depending on the binary input sequence. The output of the channel can therefore be characterized as a state machine driven by the binary input sequence, and conversely, the input sequence can be estimated or demodulated by running the signal samples at the output of the channel through an xe2x80x9cinversexe2x80x9d state machine. Because noise will obfuscate the signal samples, the inverse state machine is actually implemented as a trellis sequence detector which computes a most likely input sequence associated with the signal samples (i.e., the sequence through a trellis that is closest to the signal samples in Euclidean space).
Operation of a PR4 trellis sequence detector is understood from its state transition diagram shown in FIG. 2A. Each state 100 is represented by the last two input symbols (in NRZ after preceding), and each branch from one state to another is labeled with the current input symbol in NRZ 102 and the corresponding sample value 104 it will produce during readback. The demodulation process of the PR4 sequence detector is understood by representing the state transition diagram of FIG. 2A as a trellis diagram shown in FIG. 2B. The trellis diagram represents a time sequence of sample values and the possible recorded input sequences that could have produced the sample sequence. For each possible input sequence, an error metric is computed relative to a difference between the sequence of expected sample values that would have been generated in a noiseless system and the actual sample values output by the channel. For instance, a Euclidean metric is computed as the accumulated square difference between the expected and actual sample values. The input sequence that generates the smallest Euclidean metric is the most likely sequence to have created the actual sample values; this sequence is therefore selected as the output of the sequence detector.
To facilitate the demodulation process, the sequence detector comprises path memories for storing each of the possible input sequences and a corresponding metric. A well known property of the sequence detector is that the paths storing the possible input sequences will xe2x80x9cmergexe2x80x9d into a most likely input sequence after a certain number of sample values are processed, as long as the input sequence is appropriately constrained. In fact, the maximum number of path memories needed equals the number of states in the trellis diagram; the most likely input sequence will always be represented by one of these paths, and these paths will eventually merge into one path (i.e., the most likely input sequence) after a certain number of sample values are processed.
The xe2x80x9cmergingxe2x80x9d of path memories is understood from the trellis diagram of FIG. 2B where the xe2x80x9csurvivorxe2x80x9d sequences are represented as solid lines. Notice that each state in the trellis diagram can be reached from one of two states; that is, there are two transition branches leading to each state. With each new sample value, the Viterbi algorithm recursively computes a new error metric and retains a single survivor sequence for each state corresponding to the minimum error metric. In other words, the Viterbi algorithm will select one of the two input branches into each state since only one of the branches will correspond to the minimum error metric, and the paths through the trellis corresponding to the branches not selected will merge into the paths that were selected. Eventually, all of the survivor sequences will merge into one path through the trellis which represents the most likely estimated data sequence to have generated the sample values as shown in FIG. 2B.
In some cases, if the input sequence is not appropriately constrained through the use of a channel code, the path memories will not merge into one survivor sequence. Consider the PR4 trellis shown in FIG. 2B; an input sequence of all zeros or all ones will prevent the paths from merging which leads to multiple possible survivor sequences output by the detector. Data sequences which prevent the path memories from merging are referred to as xe2x80x9cquasi-catastrophicxe2x80x9d data sequences since they result in quasi-catastrophic errors in the output sequence. In order to avoid quasi-catastrophic errors, a channel code is typically employed which codes out of the recorded data all sequences which can prevent the path memories from merging.
Even if the quasi-catastrophic data sequences are coded out of the input sequence, the sequence detector can still make an error in detecting the output sequence if enough destructive noise is present in the read signal. The possible output sequences are different from one another by a minimum Euclidean distance; a detection error typically occurs when the signal noise breaches this minimum distance between valid output sequences. FIGS. 3A-3D illustrate the sample error sequences associated with the dominant minimum distance error events of a PR4 sequence detector in NRZ, PR4, EPR4 and EEPR4 space, respectfully. In general, a higher order sequence detector will outperform a lower order sequence detector due to the number of data samples the error event affects. Consider, for example, the first error event in the NRZ space shown in FIG. 3A. This error event generates two noise samples which corrupt two data samples (two output bits) in the PR4 space of FIG. 3B, four noise samples in the EPR4 space of FIG. 3C, and four noise samples with two having increased magnitude in the EEPR4 space of FIG. 3D. This xe2x80x9cspreading outxe2x80x9d of the error event reduces the probability of a detection error.
A minimum distance error event can occur where the data sequences diverge from a particular state in the trellis and then remerge at a later state. In a perfect system, all of the minimum distance error events will occur with equal probability. However, because the channel equalizers correlate the noise in the signal samples, the minimum length, minimum distance error events are more likely to occur. Thus, the error events shown in FIGS. 3A-3D are the xe2x80x9cdominantxe2x80x9d minimum distance error events because they are shortest in length. The first error event ((+) in NRZ), which is the shortest error event, is typically the most dominant; however, depending on the partial response polynomial employed, other error events may become the most dominant as the linear bit density increases.
An increase in performance can be achieved by employing a channel code to code out data sequences associated with the minimum distance error events (similar to coding out the quasi-catastrophic data sequences), and then to match the sequence detector to this channel code using conventional trellis coded modulation (TCM) techniques. For example, the minimum distance error events shown in FIG. 3A can be coded out by removing the bit sequences consisting of (1,0,1) or (0,1,0) from the input sequence. The state machine of a PR4 sequence detector can then be matched to this code constraint by removing the inner branches shown in FIG. 2A. With these branches removed, the minimum distance of the PR4 sequence detector increases from dmin2=2 to dmin2=4 (with the signal samples normalized to +1, 0, xe2x88x921).
The recording and reproduction of digital data through a disk storage medium can be modeled as a communication channel. Partial response signaling is particularly well suited to disk storage systems because they are bandpass channels in nature and therefore less equalization is required to match the overall response to a desired partial response polynomial. Referring to FIG. 1A, higher order partial response polynomials, such as EEPR4, are more closely matched to the channel""s natural response than lower order polynomials, particularly at higher linear densities. Thus, in addition to spreading out the error samples as shown in FIG. 3, higher order partial response channels typically provide better performance since less equalization is required to match the channel""s response to the desired partial response. However, the trade-off in performance is the cost of complexity; the number of states in the state machine equals 2n+1 which means an exponential increase in complexity as the order of the polynomial increases. A full EEPR4 state machine comprises sixteen states (n=3) compared to only four states in a PR4 state machine.
Similar to the PR4 read channel described above, matching the EPR4 state machine to a run-length limited (RLL) d=1 constraint (which prevents consecutive NRZI xe2x80x9c1xe2x80x9d bits) codes out many of the minimum distance error events of an EPR4 sequence detector, thereby providing a coding gain over an uncoded EPR4 sequence detector. However, a disadvantage to the RLL d=1 constraint is the attendant decrease in code rate, the ratio of user data bits to codeword bits which is typically 2/3 in an RLL (1,7) system. The decrease in code rate is undesirable because it decreases the user data density and hence the overall storage capacity of the disk. The user data density and storage capacity can be increased by increasing the channel data density, but this increases the bit error rate due to the effective decrease in SNR. Further, increasing the channel density requires faster read channel circuitry to compensate for the increase in the channel data rate.
Similar performance gains can be achieved with channel codes that exhibit higher code rates, but this typically leads to a more complex implementation in matching the state machine of the trellis sequence detector to the code constraint, as well as more complex encoder/decoder (ENDEC) circuitry for implementing the channel code. For example, the above-referenced co-pending patent application entitled xe2x80x9cTRELLIS CODING SYSTEM FOR DISC STORAGE SYSTEMSxe2x80x9d employs a channel code which constrains the occurrence of tribits to k-modulo-3, and forbids runs of four or longer consecutive NRZI xe2x80x9c1xe2x80x9d bits. The theoretical capacity of this code is 0.9032 with a practical code rate of 8/9 as compared to the 2/3 rate of a typical RLL d=1 code. However, the trade-off is the increase in complexity in matching the trellis state machine to the code constraint; it requires a more sophisticated time-varying state machine which changes structure at times k-modulo-3. Further, implementing the k-modulo-3 code constraint requires a more sophisticated ENDEC as compared to the ENDEC required to implement the less complex RLL d=1 code constraint.
There is, therefore, a need for a sampled amplitude read channel for use in disk storage systems that provides a performance enhancing improvement by attenuating the dominant error events of a trellis sequence detector without significantly decreasing the storage it system""s code rate and without significantly increasing the cost and complexity of the trellis sequence detector and channel ENDEC.
In a sampled amplitude read channel for disk storage systems (e.g., magnetic or optical disk drives), a post process is employed to correct errors in a preliminary sequence caused by the dominant error events of a trellis sequence detector. A sample error sequence is generated by remodulating the preliminary sequence into a sequence of estimated sample values, and subtracting this estimated sequence from the read signal sample values. The post processor comprises a bank of error filters matched to the dominant error events of the trellis sequence detector. By correlating the sample error sequence with the dominant error events, the error filters compute a Euclidean distance error metric between the samples sequence selected by the trellis sequence detector and the sample sequence that would have been selected if an error event did not occur. The minimum error metric is assigned to the symbols in the preliminary sequence that differ from the symbol sequence that would have been generated if the error event did not occur. After processing a predetermined number of the symbols in the preliminary sequence, the error metrics assigned to the symbols are used to detect and correct error events in the preliminary sequence.
In one embodiment of the present invention, the post processor is guided by an error syndrome generated from an error detection channel code. When the error syndrome indicates an error is present in a codeword block, the error metrics assigned to the symbols in the preliminary sequence are evaluated to determine the most likely error event to have caused the error. For example, the most likely error event occurs where the error metrics are consistent with a dominant error event, the error metrics are minimum, and the error event is consistent with the error syndrome.
The error detection code embodiment of the present invention approximates the performance gain provided by matching the trellis sequence detector""s state machine to the error detection code, but with a significant reduction in cost and complexity. In addition, the error detection code can be implemented with a high code rate using a relatively unsophisticated ENDEC. For example, a simple parity error detection code can be implemented with a code rate of 64/69 using a conventional 16/17 RLL ENDEC concatenated with a simple parity generator as described in the above-referenced co-pending patent application entitled xe2x80x9cSAMPLED AMPLITUDE READ CHANNEL EMPLOYING A REMOD/DEMOD SEQUENCE DETECTOR GUIDED BY AN ERROR SYNDROME.xe2x80x9d